1. Field of the Invention
The present invention relates to a memory system and data copy method therefor and, more particularly, to copying of successive pages in, e.g., a NAND flash memory, and is applied to system which performs error correction in copying.
2. Description of the Related Art
In a NAND flash memory, as disclosed in, e.g., Jpn. Pat. Appln. KOKAI Publication No. 2002-141477, a memory cell has an n-channel MOSFET structure in which, for example, a floating gate and control gate are stacked as a charge storage multilayer. A plurality of memory cells of this structure are series-connected to each other so that adjacent memory cells share sources and drains. One NAND string is formed by interposing first and second select gates respectively between a bit line and one terminal of the NAND string and between a source line and the other terminal. The NAND strings are arrayed, and the control gates of memory cells on the same row are commonly connected to a word line. The gates of the first select gates on the same row are commonly connected to the first select gate line, and those of the second select gates on the same row are commonly connected to the second select gate line.
A group of NAND strings which share the word line forms a block serving as an erase unit, and in an erase, data of all memory cells in the block are erased. In a read and write, one first select gate in a plurality of blocks is selected and rendered conductive to connect series-connected memory cells to a bit line. In this state, a selection voltage is applied to one word line, and a non-selection voltage is applied to the remaining word lines on the same NAND string. Each bit line is connected to a sense amplifier and a write bias circuit (to be referred to as a page buffer including a data buffer which holds read data and write data). A read and write are executed for pages which share a selected word line. One page is made up of, e.g., 2,112 bytes, and one block is made up of, e.g., 128 KB.
A host accesses data stored in a memory cell via an I/O bus. Assuming that the bit width of the I/O bus is, e.g., 8 bits (1 byte), the host accesses the page buffer byte by byte, similar to an SRAM.
In the NAND flash memory, even an unselected word line (control gate) is biased in a read or write by applying a high voltage, the disturbing characteristic is strict, and error correction is often required for a read. The size of the erase unit (block) is larger than that of the write unit (page), and when given page data is erased for overwrite, an entire block containing the page is erased. To prevent this, the remaining page data in the block must be backed up in another block before an erase. This results in frequent copying of successive pages (page copy) in the NAND flash memory.
The NAND flash memory performs sense operation for each page, and can easily implement a page copy function of directly writing read data in another page when a page copy is done without any error correction. If no error correction is performed for read data and the read data is erroneous, the erroneous data is directly written into a new page. In this case, repetitive page copying may generate many error bits which cannot be corrected by general error correction in a read.
In order to avoid generation of many error bits, a copy method is sometimes employed in which error correction is done for data read in a page copy, and if an error bit is detected, the data is corrected and then written at a new page address. At this time, a page copy consists of three sequences: reading a target page, error correction of read data, and writing to a write destination. Of these sequences, reading and writing require access to a memory cell, and error correction requires access not to a memory cell but to an error correction circuit. Reading and writing can be batch-processed for each page, but in error correction, data of a page buffer must be sequentially transferred to an ECC circuit 11 via a bus (e.g., 8 bits). For example, when the page size is 2,112 bytes and the bus width is 8 bits, 2,112 cycles of “data read+error calculation and update of corrected data” are necessary. For an access cycle of 50 ns, these cycles require about 100 μs (50 ns×2,112). Assuming that a read takes 25 μs and a write takes 200 μs, this page copy takes 1.5 times as long as for a page copy free from any error correction.
As described above, in the conventional memory system and the data copy method therefor, if no error correction is done in a read of a page subjected to page copying, repetitive page copying causes a data copy error, degrading the data reliability. Error correction for preventing the degradation makes page copying very slow.